This invention relates to MOSgated semiconductor devices and more specifically, relates to such devices with a trench geometry and a remote contact structure. This application claims priority to related U.S. Provisional Application No. 60/104,148, now U.S. Pat. No. 6,476,443 B1 filed Oct. 14, 1998 and entitled MOSGATED DEVICE WITH TRENCH STRUCTURE AND REMOTE CONTACT AND PROCESS FOR ITS MANUFACTURE.
MOSgated devices are well known and may have a planar channel geometry or a trench channel geometry.
In the planar geometry version, spaced channel regions are diffused into the surface of a chip and MOSgates cover the invertible channel regions which are coplanar with one another. Such structures are useful over a wide range of breakdown voltages.
In the trench geometry version, invertible channel regions are formed along the vertical walls of U-shaped trenches etched into the silicon surface. A source contact is connected to the channel region and source region for each separate trench unit. Trench devices are preferably used for lower breakdown voltage ratings, for example, less than about 100 volts.
Both planar geometry devices and trench geometry devices may be formed with channel regions of a spaced polygonal or spaced stripe arrangement.
Trench geometry devices have an inherently lower capacitance between gate and drain, and thus a lower charge QGD than planar devices. Since an important figure of merit of a MOSFET is the product of QGD and the on-resistance RDSON, trench devices are frequently desired for low voltage applications requiring a minimum switching loss such as the MOSFETs used in low voltage power supplies for supplying power from a battery to a portable electronic device such as a lap top computer.
Trench device geometries have not permitted the best trench density for minimizing the RDSON. Therefore, while the trench device has a low QGD, complex manufacturing processes are needed to produce a low RDSON as well.
Thus, it is desirable to provide a trench geometry MOSgated device such as a MOSFET, which has a minimized QGD and RDSON but is capable of inexpensive and reliable production techniques.
In accordance with the present invention, a novel trench structure and manufacturing process is provided in which both a very low QGD and RDSON is provided through the use of a common polysilicon layer for a plurality of adjacent trenches, with contacts to the source and channel region being remote from the trench areas. As a result, the trenches can be more closely spaced, to increase total channel width per unit area. The QGD is also reduced by the use of a unique trench mesa height and control of the trench bottom relative to the P/N junction which defines the bottom of the invertible channel along the walls of the trench. More specifically, a trench depth (or mesa height) of about 1.8 microns is used, with the trench bottom penetrating the P/N junction by about 0.2 to 0.25 microns.
The novel trench structure is also preferred to have a length less than about 20 microns and a width of about 0.6 microns. The trenches are arranged in parallel, coextensive groups with a spacing greater than about 0.6 microns. The trenches are filled with a common polysilicon layer which acts as the device gate. Each parallel set of trenches are spaced from an adjacent set by a strip of untrenched area running perpendicular to the elongated trenches. The source/base contacts are formed in this strip, remotely from the trench structures, but connected to the channel region and source region for each trench.
By making contact only to the source region, a bidirectional conductive device can be formed.
The novel device lends itself to a simplified manufacturing process having a reduced number of masks and critical mask alignments and has a minimized figure of merit.